Three Power Saving Techniques Using PCI Express IP
The use of PCI Express for connectivity in computing applications (servers, networking, laptops, etc.) has been prevalent for some time, while usage in smaller, battery-powered devices (phones, tablets, watches, etc.) is becoming more widespread. The increasing data traffic between devices in a computing application environment is causing a large power footprint and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery- powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to switch back to normal operating mode. Designers using PCI Express are positively influencing their target application’s power footprint by integrating PCI Express IP into their SoCs while leveraging advance power management techniques in addition to the power saving techniques provided by the protocol. Clock gating techniques are used to handle dynamic power consumption but without any effect on static power consumption. Power gating techniques are ideal for saving maximum power as it saves the rising static power consumption due to shrinking feature sizes. In deep power saving modes, power gating a PCI Express IP typically requires PCI Express link re-training or reconfiguration, which increases resume times not desirable in many scenarios and a significant challenge. This paper uses PCI Express IP as an example to describe three power saving techniques and how designers are using the protocol’s and design tools’ power management features to deliver power-efficient SoCs for devices requiring fast resume times.
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