Industry Trends

Join CadenceLIVE Silicon Valley on June 8-9 for over 80 exciting and dynamic sessions across 11 tracks. Hear top technologists from companies such as Microsoft, NVIDIA, BAE Systems, Meta, Samsung, Renesas, Broadcom, Texas Instruments, and more. Learn new ways to solve your design challenges.
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Join designers, researchers, tool developers & vendors for superb training, education, exhibits & networking at the event for the design & design automation of electronic chips to systems. DAC topics include IP, AI, EDA, Security, Cloud & Embedded Systems.
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Join our webinar to learn how to use an initial SiP file from the Cadence^® Allegro^® Package Designer to enable IC-package co-design in the Cadence Virtuoso^® platform and keep the SiP database and OpenAccess database in sync in the Virtuoso platform.
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* High performance PHY with optional controller
* Delivered as hard macro with I/Os to exact customer floorplan
* Easy to close timing, integrate and test
* Available in variety of protocols and TSMC processes
 

Join this webinar to learn how a full Cadence® design and analysis flow can reduce your time to signoff for PCIe 6.0 devices by up to two months. It will present solutions for the signal integrity (SI) and power integrity (PI) challenges associated with the new PCIe 6.0 standard, along with early what-if analysis scenarios using system-level exploration technology that guides design teams toward optimized solutions. 
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Come talk to our Cadence Tensilica® experts at Autosens Detroit & find out how our IP solutions & On-Device AI enable the automotive of the future. 
Attend Cadence Presentation: 
What sensing & On-Device AI are required for the automotive of the future?
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Join us for this webinar where Thierry Kouthon of Rambus and Ann Keffer of Siemens will discuss hardware solutions for securing automotive electronics and how functional safety tools from Siemens meet the requirements of ISO 26262.
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Learn best practices for proper EM analysis to quickly achieve accurate simulation results. Review CAD techniques for leveraging EM simulation to more rapidly analyze and optimize designs versus sheer brute force of large numbers for distinct EM simulations.
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Join Cadence experts and learn about growing system analysis challenges among 3D-IC designers related to signal, power, and thermal integrity, and how simulation during system planning and signoff helps to accelerate the 3D-IC design cycle.
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This webinar introduced the operational challenges identified during the devices security lifecycle, especially across large and heterogeneous fleets at scale.

Webinar held on February 25, 2022.

Ask for the replay here >>