Semiconductor IP Industry News
November, 2019

Arm Veteran to Enable Next-Generation High-Performance Processor Development

SAN MATEO, Calif., Nov. 26, 2019 - SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Ann Chin has joined the company as vice president and co-general manager of the SiFive IP business unit. Chin joins ...

MOUNTAIN VIEW, California, Nov. 25, 2019 -

Highlights:

• Tools certified for the latest version of TSMC's N5/N5P DRM and SPICE model
• Synopsys power optimization enabled to support ultra-low power requirement of mobile devices
• Implementation vs. signoff correlation, certified for timing and extraction, reduces time-to-market
• Collaboration also extended to certification on TSMC's N6 process technology for ...

Broad Portfolio of Reusable Plug and Play VIP Fills Verification Coverage Gaps, Supports Code Coverage, Functional Coverage

SAN JOSE, CALIF. - November 21, 2019 – SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced its broad portfolio of portable, platform-independent VIP ensures a thorough and seamless ...

November 20, 2019 - Moortec the go-to leaders of in-chip technologies will be showcasing their PVT Monitoring Subsystem IP at this week's CSIA-ICCAD which is taking place at the Nanjing International Expo Convention Center.

The Conference will discuss the opportunities and challenges faced by the IC industry and enhance the ...

SEOUL, South Korea – November 19, 2019 – With Korea the world’s largest manufacturer of memory semiconductors and leading in 300mm fab construction in 2019, the region is paving the way to SEMICON Korea 2020 as more than 500 companies and 55,000 visitors are expected to gather February 5-7 ...

Arasan Chip Systems a leading provider of semiconductor IP for mobile and automobile SoCs today announced the immediate availability of its MIPI D-PHY IP supporting the D-PHY v2.1 specification for speeds upto 4500 Mbps for TSMC 28nm SoC designs

Nov 18th, 2019, San Jose, CA: Arasan today announced the immediate availability ...

eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading global manufacturer of electronic interconnect solutions, will demonstrate eSilicon’s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for challenging data center applications over a five-meter Samtec cable assembly.

What
eSilicon and Samtec have co-developed system-level ...

SAN JOSE, Calif., November 13, 2019—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence® UltraLink™ D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments. The UltraLink D2D PHY IP is an enabling technology for chiplet and system-in-package ...

Highlights

- Acquisition of eSilicon IP will expand Synopsys' existing DesignWare Embedded Memory and Interface IP portfolio
- Acquisition will enable Synopsys to further scale its IP offering to address requirements of growing markets such as artificial intelligence (AI) and cloud
- Addition of experienced R&D engineering team will accelerate development of physical ...

SAN JOSE, CALIF. –– November 6, 2019 –– SmartDV™ Technologies will exhibit at SemIsrael Expo 2019 in Airport City, Israel, November 19 and ICCAD China 2019 November 21-22 in Nanjing, China.

At both events, SmartDV will showcase why it is the Proven and Trusted choice for Verification and Design Intellectual Property ...

Santa Clara Calif. and Hsinchu, Taiwan, Nov. 05, 2019 - GLOBALFOUNDRIES® (GF®) and SiFive, Inc. announced today at GLOBALFOUNDRIES Technology Conference (GTC) in Taiwan that they are working to extend high DRAM performance levels with High Bandwidth Memory (HBM2E) on GF’s recently announced 12LP+ FinFET solution, with 2.5D packaging design ...

Nov 1st, 2019, San Jose, CA: Arasan today announced the immediate availability of its MIPI D-PHY IP compliant to the D-PHY specification Version 2.1 which can support speeds of upto 4.5ghz The D-PHY v2.1 IP is available as standard Tx / Rx pair or as Tx only or Rx only ...