Semiconductor IP Industry News
March, 2019

April 3, 2019, San Jose, Calif. - eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, is giving a presentation on ASIC and deep learning at the State of AI and ML-Spring 2019 conference, to be held in Santa Clara, Calif.

Who:
Dr. Carlos Macian, Sr. ...

SAN JOSE, Calif. - March 27, 2019 - Cadence Design Systems, Inc. (NASDAQ: CDNS) hosts its CDNLive Silicon Valley user conference from April 2-3, 2019, in Santa Clara, California. CDNLive Silicon Valley offers Cadence® users, developers and industry experts an opportunity to connect, share and inspire one another and discover ...

Semiconductor, Electronic System Design Ecosystem Community Invited to Attend; Event Open Free of Charge to ESD Alliance and SEMI Members

MILPITAS, CALIF. - March 26, 2019 - The Electronic System Design Alliance, a SEMI Strategic Association Partner hosts a Fireside Chat with Jim Hogan, managing partner of Vista Ventures, LLC., and Paul ...

Latest PowerVR tools include specific support for Unity™ and Unreal Engine 4™

SAN FRANCISCO, March 19, 2019 - Game Developers Conference (GDC), USA -- Imagination Technologies (booth S763), a leading technology provider for graphics, neural network acceleration and connectivity, announces new and enhanced tools to help developers optimise Android™ graphics performance ...

MOUNTAIN VIEW, California, March 22, 2019 - Synopsys, Inc. announced the availability of the industry's first Subsystem Verification Solution, Verification IP (VIP), and UVM source code test suite to support the latest USB4 specification. USB4 includes two-lane operation using the existing USB Type-C™ connector that can carry up to 40Gbps ...

March 20, 2019, Barcelona, Spain - eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, with the Polytechnic University of Catalonia, Barcelona, Spain are presenting two papers on advanced floor planning techniques at DATE 2019, Florence, Italy.

Who:

Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Department of ...

Cadence VIP and TripleCheck technology support for the next-generation USB standard enables early adoption of the protocol

SAN JOSE, Calif., March 14, 2019 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry’s first Verification IP (VIP) in support of the recently announced USB4 standard. The Cadence® ...

Native SystemVerilog VIP for USB Features Built-in Coverage, Verification Plan, Protocol-Aware Debug, and Source Code Test Suites

MOUNTAIN VIEW, Calif., March 14, 2019 - Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first Subsystem Verification Solution, Verification IP (VIP), and UVM source code test suite to support ...

March 12, 2019, San Jose, Calif. - eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will demonstrate its 7nm FinFET-class SerDes IP product at OCP 2019.

What
SerDes Demonstration: Samtec booth at OCP, San Jose Convention Center
Thursday-Friday
March 14-15, 2019

Using Samtec ExaMAX Backplane Connector paddle cards ...

Silicon proven IP path significantly reduces risk, time-to-market and overall cost

Belgium, February 26, 2019 – Graphcore (www.graphcore.ai), the technology company that has developed a completely new type of processor, the Intelligence Processing Unit (IPU), which lets artificial intelligence (AI) innovators create next generation AI applications, selected TakeCharge® technology from Sofics ...

Interoperability demonstrated between eSilicon 7nm SerDes and Intel Stratix 10 FPGA

SAN DIEGO, Calif. - March 5, 2018 - eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today at the OFC conference in San Diego an interoperability demonstration in their booth #5416. The ...

Complete LPDDR5 IP Solution Includes Cadence PHY, Controller and Verification IP

SAN JOSE, Calif., March 4, 2019 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced early availability of the complete, silicon-proven Cadence® Denali® Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology. Offering up to 1.5X faster bandwidth than ...

Enables Development of Isolated, Secure Environments for High-Performance Applications

MOUNTAIN VIEW, Calif., Feb. 27, 2019 -

Highlights:

• New Enhanced Security Package option for ARC HS3x and HS4x processors enables development of secure environments in high-performance embedded applications
• Data integrity protection detects fault injection attacks to help prevent hackers from bypassing secure ...