Traditional data conversion of signals with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) use a synchronous sampling clock to convert signals between the analog and digital domains. For high performance data converters operating at high speeds (>100MS/s) or high resolution (>10bits), the purity of the sampling clock is critical to achieve optimal performance. This technical article describes the specific requirements on the data converter clock source for high performance data converters, and provides guidelines on how to minimize the noise contribution of clock sources. For simplicity, this article focuses on ADC clocking, but the same concepts and guidelines apply to DAC clocks.

**Clock Jitter**

Jitter is the timing error of a clock source compared to an ideal synchronous edge as measured in the time domain. Clock jitter can have both random (e.g. Gaussian) and deterministic components (e.g. data dependent jitter), where both sources of jitter degrade the performance of data converters. Random clock jitter typically raises the noise floor of the data converter and results in degraded signal-to-noise ratio (SNR), whereas deterministic clock jitter often results in output frequency spurs and increased distortion. This section provides some technical background on clock jitter, and then explains in detail how random and deterministic jitter impact performance of data converters.

**Clock Jitter Metrics**

Clock jitter can be evaluated through a variety of metrics, and three metrics are commonly used: absolute jitter, period jitter, and cycle-to-cycle jitter. These three metrics are typically represented as a peak-to-peak (pk-pk) or root mean square (rms) value. Absolute jitter, also referred to as long-term jitter, represents the absolute difference in the clock edge from an ideal, jitter-free clock. Period jitter represents the difference in the clock period of the clock source from the ideal clock period. Finally, cycle-to-cycle jitter represents the difference between two consecutive periods of the clock source. Figure 1 demonstrates graphically these three commonly used clock jitter metrics.

**Figure 1: Timing diagram defining instantaneous long-term, period, and cycle-to-cycle jitter**

These three metrics are all related to one another. Cycle-to-cycle jitter can be thought of as the discrete-time derivative of period jitter, which can be thought of as the discrete-time derivative of long-term jitter. For data converters, which one of these metrics is the most relevant depends on the input signal being converted. The next section of this article derives the relationship between Gaussian long-term sampling jitter and ADC SNR assuming a noiseless ADC.

**Impact of clock jitter on data converter performance**

**Figure 2: Relationship between clock jitter and voltage error for a data converter**

Figure 2 shows graphically how clock jitter can result in a voltage error in a sampled ADC. If the input to an ADC, V_{in}, is a time-varying signal, then a sampling time error of Δt results in a change in sampled voltage of ΔV. If we assume an input sinusoidal signal V_{in} with amplitude of V_{A} and frequency of f_{in}, we can represent the waveform with the following equation:

(1) V _{in}=V_{A} sin(2πf_{in}^{t})

The slope of the input signal can be represented by the following equation:

(2) dVin/dt=2πf_{in} V_{A}cos(2πf_{in} t)

From equation (2), it is possible to determine that at time ti, the impact of timing jitter Δt results in a sampling voltage error 2πf_{in} V_{A} cos(2πf_{in} t_{i})?t. When the cosine term equals 1, this results in a maximum of voltage error, giving a peak voltage error of 2πf_in V_{A} ?t. The rms voltage error can be shown to be equal to 1/√2 2πf_{in} V_{A} ?t. From this result, we see that increasing the clock jitter results in an increased voltage error. Moreover, increasing the amplitude of the input voltage, or increasing its frequency also results in increased voltage error for a fixed clock jitter.

If we consider long-term clock jitter to have a Gaussian noise source with a standard deviation of t_{j}, one can derive the resulting SNR of the ADC for a full-scale sinusoidal input solely considering the long-term jitter of the sampling clock:

(3) SNR=20log(?1/(2πf_{in} t_{j} ))

Figure 3 shows graphically the relationship between rms long-term clock jitter, input frequency and SNR. For fixed clock jitter, as the input frequency increases, the ADC SNR decreases. For high performance ADCs, sub-picosecond clock jitters are often required to achieve optimal performance. For example, for a noiseless ADC to achieve an SNR of 70dB with a 100 MHz, full-scale input frequency requires long-term clock jitter of 0.5psrms. This jitter requirement is typical for a 200MS/s, 12bit ADC like the CAT-ADP12B200M-65, and such a low jitter clock could be generated by the CAT-PLI-DDC-65. As ADCs are not noiseless the jiter requirement is more stringent, so that the jitter due to the clock source does not degrade SNR significantly.

**Figure 3: Maximum SNR vs. input frequency for a noiseless ADC in the presence of a full-scale sinusoidal input with rms long-term clock jitter**

**Deterministic clock jitter and clock skew**

The previous analysis assumed that clock jitter had a Gaussian profile. In practice, clock sources can have deterministic spurs and jitter. Spurs in the data converter clock source can result in spurs at the output of the data converter, degrading performance and reducing the data converter spurious free dynamic range (SFDR).

Another source of error in ADC clocking is non-ideal clock skew between channels in time-interleaved ADCs. Very high speed ADCs often employ a time-interleaved architecture whereby multiple ADC channels are operated in parallel at a lower clock frequency that the effective sampling rate and their sample times are evenly staggered from one another. For example, four, 200 MS/s, 12-bit ADCs can be time-interleaved to realize an 800 MS/s, 12-bit ADC. In time-interleaved ADCs, the parallel ADCs take turns sampling the input signal, and their sampling instants must be equally staggered in time, otherwise deterministic sampling jitter and clock spurs will result. Figure 3 shows a block diagram of a four-channel time interleaved ADC. To optimize performance of time-interleaved, high performance ADCs, it can be necessary to calibrate each channel’s clock skew.

**Figure 4: Time-interleaved ADC consisting of four ADCs in parallel with their sample times evenly staggered**

**Recommendations for Reducing Clocking Noise in Data Converter Interfaces**

When integrating data converters in a large SoC, there are several steps that should be taken to optimize clock routing and the clock network outside of the core data converter. These steps include using differential off-chip clock input, sufficiently buffering the clock signal within the SoC, shielding analog signals from both the clock as well as other noisy wires on-chip, and precisely controlling the sampling or update time. These techniques are shown graphically in Figure 4.

**Figure 5: Block diagram of SoC employing techniques to minimize clocking noise in data converters**

**Differential Off-chip Clock Inputs**

For high performance ADCs, differential analog inputs are often used to improve power supply rejection, reduce spurs, and reduce sensitivity to interferers. For similar reasons, it is advantageous to use a differential off-chip clock signal. A differential clock input has the added benefit that it readily allows for a low amplitude clock input with amplitude of only a few hundred milli-Volts, reducing coupling into sensitive analog circuits.

**Buffering Clock Network within SoC**

Once the differential clock input has been converted to an internal digital clock, it is important to sufficiently buffer the clock network within the SoC to ensure a fast rise and fall time; however, as each buffer adds jitter, it is important to not insert too many buffers between the low jitter clock source and the data converter. Moreover, it is important to use a low noise power supply for the clock buffers.

**Shielding Sensitive Analog Signals and Clock Network**

Within an SoC, there are many wires which can couple into sensitive analog or clock signals and result in reduced performance. A noisy wire coupling onto a clock can slightly change the sampling time, resulting in increased sampling jitter and reduced performance. Thus, it is recommended that both sensitive analog signals as well as the data converter clock network be shielded from each other as well as from potential noise sources.

**Companion Phase-Locked Loop**

For high performance data converters, it can be advantageous to use a companion phase-locked loop (PLL) to generate an internal sampling clock for the data converter. When using a companion PLL, the SoC only requires a low frequency reference clock from which the PLL generates the data converter clock. One common application of a companion PLL is to generate a low jitter, high frequency clock from a low cost, low frequency crystal oscillator.

Cambridge Analog Technologies offers companion PLLs for all of our ADCs and DACs. Our companion PLLs can also be used to generate a clock for the rest of the SoC. When the companion PLL is used in this manner, it is possible to design the system such that the ADC sampling instant is at a quiet time prior to the rest of the SoC logic being evaluated. A companion PLL is offered in our 40nm AFE, CAT-AFE-12B50M-40LP, which includes up to four, 50 MS/s I/Q ADCs and two, 100 MS/s I/Q DACs in TSMC 40nm.

**CAT’s Sabre ^{TM} Family of PLL IP for High Performance Systems**

CAT also offers high performance PLLs that complement our high performance, ultra-low power ADCs and DACs. CAT’s PLLs can also be used independently in SoCs for system clocking, skewing/deskewing, and many other applications. CAT’s PLLs are based on Sabre^{TM} technology that combines the efficiency, portability, and flexibility of digital standard cells with CAT’s proprietary mixed-signal precision circuits to create a solution that offers best-in-class jitter, power, area, and lock-times when compared to both analog and digital PLLs. CAT’s exclusive all-digital PLL architecture is offered over a wide range of performance specifications, and easily portable between foundries and CMOS process nodes.

CAT’s Sabre^{TM} PLLs are well suited for complex SoCs, where it can be extremely difficult to main high performance due to coupling through the substrate and supplies of adjacent digital logic. CAT’s PLLs are designed to ensure a robust clock, even in harsh embedded environments, and the PLLs operate directly off of core power supplies. In addition, key features of CAT’s PLLs are compact die area, ultra-fast lock, low power consumption, and extreme flexibility and programmability due to the digital core.

**Summary**

High performance data converters require low jitter sampling clocks to maximize performance. This article demonstrated the mathematic relationship between Gaussian long-term jitter and ADC SNR, and explained how deterministic jitter and clock skew can introduce spurs, degrading SFDR. In complex SoCs, there are several design steps that should be taken to maximize performance of the clock network, including shielding sensitive signals as well as using a differential clock input. Cambridge Analog Technologies offers companion and standalone digital PLLs which achieve extremely low jitter and are suitable for high performance data converters or other high performance applications.